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FEATURES 44 V Supply Maximum Rating VSS to VDD Analog Signal Range Single/Dual Supply Specifications Wide Supply Ranges (10.8 V to 16.5 V) Microprocessor Compatible (100 ns WR Pulse) Extended Plastic Temperature Range (-40 C to +85 C) Low Leakage (20 pA Typ) Low Power Dissipation (28 mW Max) Available in DIP, SOIC, PLCC, and LCCC Packages Superior Alternative to: DG526, DG527
CMOS Latched 8-/16-Channel Analog Multiplexers ADG526A/ADG527A
FUNCTIONAL BLOCK DIAGRAM
ADG526A
S1 S1A DA S8A D S1B DB S16 DECODER/ LATCHES S8B DECODER/ LATCHES
ADG527A
WR
WR
A0 A1 A2 A3 EN RS
A0 A1 A2 EN RS
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG526A and ADG527A are CMOS monolithic analog multiplexers with 16 channels and dual 8 channels respectively. On-chip latches facilitate microprocessor interfacing. The ADG526A switches one of 16 inputs to a common output depending on the state of four binary addresses and an enable input. The ADG527A switches one of eight differential inputs to a common differential output depending on the state of three binary addresses and an enable input. Both devices have TTL and 5 V CMOS logic compatible digital inputs. The ADG526A and ADG527A are designed on an enhanced LC2MOS process which gives an increased signal capability of VSS to VDD and enables operation over a wide range of supply voltages. The devices can comfortably operate anywhere in the 10.8 V to 16.5 V single or dual supply range. These multiplexers also feature high switching speeds and low RON.
1. Single/Dual Supply Specifications with a Wide Tolerance: The devices are specified in the 10.8 V to 16.5 V range for both single and dual supplies. 2. Easily Interfaced: The ADG526A and ADG527A can be easily interfaced with microprocessors. The WR signal latches the state of the Address control lines and the Enable line. The RS signal clears both the address and enable data in the latches resulting in no output (all switches off). RS can be tied to the microprocessor reset pin. 3. Extended Signal Range: The enhanced LC2MOS processing results in a high breakdown and an increased analog signal range of VSS to VDD. 4. Break-Before-Make Switching: Switches are guaranteed break-before-make so that input signals are protected against momentary shorting. 5. Low Leakage: Leakage currents in the range of 20 pA make these multiplexers suitable for high precision circuits.
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
Dual Supply
Parameter
ADG526A/ADG527A-SPECIFICATIONS
(VDD = +10.8 V to +16.5 V, VSS = -1O.8 V to -16.5 V unless otherwise noted.)
ADG526A/ADG527A ADG526A K Version B Version T Version -40 C to -40 C to -55 C to 25 C +85 C 25C +85 C 25 C +125 C Unit VSS VDD 280 450 300 RON Drift RON Match IS (OFF), Off Input Leakage ID (OFF), Off Output Leakage ADG526A ADG527A ID (ON), On Channel Leakage ADG526A ADG527A IDIFF, Differential Off Output Leakage (ADG527A Only) 0.6 5 0.02 1 0.04 1 1 0.04 1 1 VSS VDD VSS VDD 280 450 300 0.6 5 0.02 1 0.04 1 1 0.04 1 1 VSS VDD VSS VDD 280 450 300 0.6 5 0.02 1 0.04 1 0.04 1 VSS VDD V min V max typ max max max %/C typ % typ nA typ nA max nA typ nA max nA max nA typ nA max nA max nA max 2.4 0.8 1 8 200 300 50 25 200 300 200 300 100 V min V max A max pF max ns typ ns max ns typ ns min ns typ ns max ns typ ns max ns min ns min ns min ns min dB typ dB min pF typ pF typ pF typ pC typ mA typ mA max A typ mA max mW typ mW max Comments
ANALOG SWITCH
Analog Signal Range RON -10 V VS +10 V, IDS = 1 mA; Test Circuit 1 VDD = 15 V ( 10%), VSS = -15 V ( 10%) VDD = 15 V ( 5%), VSS = -15 V ( 5%) -10 V VS +10 V, IDS = 1 mA -10 V VS +10 V, IDS = 1 mA V1 = 10 V, V2 = 10 V; Test Circuit 2 V1 = 10 V, V2 = V1 = 10 V, V2 = 10 V, Test Circuit 3
600 400
600 400
600 400
50 200 100 200 100 25 2.4 0.8 1
50 200 100 200 100 25 2.4 0.8 1
50 200
10 V; Test Circuit 4
200
V1 = 10 V, V2 =
10 V; Test Circuit 5
DIGITAL CONTROL VINH, Input High Voltage VINL, Input Low Voltage IINL or IINH CIN Digital Input Capacitance
VIN = 0 to VDD
8
8 200 300 50 25 200 300 200 300 100
DYNAMIC CHARACTERISTICS* 200 tTRANSITION 300 50 tOPEN 25 200 tON (EN, WR) 300 200 tOFF (EN, RS) 300 100 tW Write Pulsewidth tS Address Enable Setup Time tH Address Enable Hold Time tRS Reset Pulsewidth OFF Isolation 68 50 5 44 22 4 0.6
V1 = 10 V, V2 = Test Circuit 7 Test Circuit 8 and 9
10 V; Test Circuit 6
400 10 400 400 120 100 10 100
400 10 400 400 120 100 10 100
400 10 400 400 130 100 10 100
Test Circuit 8 and 10 See Figure 1 See Figure 1 See Figure 1 See Figure 2 VEN = 0.8 V, RL = 1 k, CL = 15 pF, VS = 7 V rms, f = 100 kHz VS = 7 V rms, f = 100 kHz VEN = 0.8 V VEN = 0.8 V RS = 0 , VS = 0 V; Test Circuit 11 VIN = VINL or VINH VIN = VINL or VINH
68 50 5 44 22 4 0.6 1.5 20 0.2 10 28
68 50 5 44 4 0.6 1.5 20 0.2 10 28
CS (OFF) CD (OFF) ADG526A ADG527A QINJ, Charge Injection POWER SUPPLY IDD ISS Power Dissipation
1.5 20 0.2 10 28
*Sample tested at 25 C to ensure compliance. Specifications subject to change without notice.
-2-
REV. B
ADG526A/ADG527A Single Supply
Parameter ANALOG SWITCH Analog Signal Range RON
(VDD = 10.8 V to 16.5 V, VSS = GND to 0 V unless otherwise noted.)
ADG526A/ADG527A ADG526A K Version B Version T Version -40 C to -40 C to -55 C to 25 C +85 C 25C +85 C 25 C +125 C Unit VSS VDD 500 700 0.6 5 0.02 1 0.04 1 1 0.04 1 1 VSS VDD VSS VDD 500 700 0.6 5 0.02 1 0.04 1 1 0.04 1 1 VSS VDD VSS VDD 500 700 0.6 5 0.02 1 0.04 1 0.04 200 100 25 1 200 VSS VDD V min V max typ max %/C typ % typ nA typ nA max nA typ nA max nA max nA typ nA max nA max nA max V1 = 10 V/0 V, V2 = 0 V/10 V; Test Circuit 5
Comments
0 V VS 10 V, IDS = 0.5 mA; Test Circuit 1 0 V VS 10 V, IDS = 0.5 mA 0 V VS 10 V, IDS = 0.5 mA V1 = 10 V/0 V, V2 = 0 V/10 V; Test Circuit 2 V1 = 10 V/0 V, V2 = 0 V/10 V; Test Circuit 3
1000
1000
1000
RON Drift RON Match IS(OFF), Off Input Leakage
50
50
50
ID (OFF), Off Output Leakage ADG526A ADG527A ID (ON), On Channel Leakage ADG526A ADG527A IDIFF, Differential Off Output Leakage (ADG527A only) DIGITAL CONTROL VINH, Input High Voltage VINL, Input Low Voltage IINL or IINH CIN Digital Input Capacitance
200 100
200 100
200
V1 = 10 V/0 V, V2 = 0 V/10 V; Test Circuit 4
200 100 25
2.4 0.8 1 8 8 300 450 50 25 250 450 250 450 100
2.4 0.8 1 8 300 450 50 25 250 450 250 450 100
2.4 0.8 1
V min V max A max pF max ns typ ns max ns typ ns min ns typ ns max ns typ ns max ns min ns min ns min ns min dB typ dB min pF typ pF typ pF typ pC typ mA typ mA max mW typ mW max
VIN = 0 to VDD
DYNAMIC CHARACTERISTICS* 300 tTRANSITION 450 50 tOPEN 25 250 tON (EN, WR) 450 250 tOFF (EN, RS) 450 100 tW Write Pulsewidth tS Address Enable Setup Time tH Address Enable Hold Time tRS Reset Pulsewidth OFF Isolation 68 50 5 CS (OFF) CD (OFF) ADG526A 44 ADG527A 22 QINJ, Charge Injection 4 POWER SUPPLY IDD Power Dissipation 0.6
600 10 600 600 120 100 10 100
600 10 600 600 120 100 10 100
600 10 600 600 130 100 10 100
V1 = 10 V/0 V, V2 = 0 V/10 V; Test Circuit 6 Test Circuit 7 Test Circuits 8 and 9 Test Circuits 8 and 10 See Figure 1 See Figure 1 See Figure 1 See Figure 2 VEN = 0.8 V, RL = 1 k, CL = 15 pF VS = 3.5 V rms, f = 100 kHz VEN = 0.8 V VEN = 0.8 V RS = 0 , VS = 0 V; Test Circuit 11 VIN = VINL or VINH
68 50 5 44 22 4 0.6 1.5 1.5 11 25 25
68 50 5 44 4 0.6 1.5 11 25
11
*Sample tested at 25C to ensure compliance. Specifications subject to change without notice.
REV. B
-3-
ADG526A/ADG527A
TIMING DIAGRAMS
3V
3V WR 0V 1.5V
RS 0V
1.5V
tW tS
3V EN A0, A1, A2, (A3) 0V 2.0V 0.8V
t RS
tH
SWITCH OUTPUT
t OFF (RS)
VO 0V 0.8VO
Figure 1.
Figure 2.
Figure 1 shows the timing sequence for latching the switch address and enable inputs. The latches are level-sensitive; therefore, while WR is held low, the latches are transparent and the switches respond to the address and enable inputs. This input data is latched on the rising edge of WR.
ABSOLUTE MAXIMUM RATINGS 1
(TA = 25C unless otherwise noted.)
Figure 2 shows the Reset Pulsewidth, tRS, and Reset Turn-off Time, tOFF (RS). Note: All digital input signals rise and fall times measured from 10% to 90% of 3 V, tR = tF = 20 ns.
ORDERING GUIDE
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25 V Analog Inputs2 Voltage at S, D . . . . . . . . . . . . . . . . VSS - 2 V to VDD + 2 V . . . . . . . . . . . . . . . . . . . . . or 20 mA, Whichever Occurs First Continuous Current, S or D . . . . . . . . . . . . . . . . . . . 20 mA Pulsed Current S or D 1 ms Duration, 10% Duty Cycle . . . . . . . . . . . . . . . 40 mA Digital Inputs2 Voltage at A, EN, WR, RS . . . . . . . . . VSS - 4 V to VDD + 4 V . . . . . . . . . . . . . . . . . . . . . or 20 mA, Whichever Occurs First Power Dissipation (Any Package) Up to 75C by . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 mW Derates above 75C by . . . . . . . . . . . . . . . . . . . . . 6 mW/C Operating Temperature Commercial (K Version) . . . . . . . . . . . . . . . -40C to +85C Industrial (B Version) . . . . . . . . . . . . . . . . . -40C to +85C Extended (T Version) . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condition for extended periods may affect device reliability. 2 Overvoltage at A, EN, WR, RS, S, or D will be clamped by diodes. Current should be limited to the maximum rating above.
Model1 ADG526AKN ADG526AKR ADG526AKP ADG526ABQ ADG526ATQ3 ADG526ATE3 ADG527AKN ADG527AKR ADG527AKP ADG527ABQ
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -55C to +125C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Option2 N-28 R-28 P-28A Q-28 Q-28 E-28A N-28 R-28 P-28A Q-28
NOTES 1 To order MIL-STD-883, Class B processed parts, add /883B to part number. See Analog Devices Military Products Databook (1990) for military data. 2 E = Leadless Ceramic Chip Carrier; N = Narrow Plastic DIP; P = Plastic Leaded Chip Carrier; Q = CERDIP; R = 0.3" Small Outline IC (SOIC). 3 Standard Military Drawing (SMD) assigned by DESC. SMD numbers are: 5962-89710013X (ADG526ATE/883B) 5962-8971001XX (ADG526ATQ/883B)
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG526A/ADG527A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-4-
REV. B
ADG526A/ADG527A
TRUTH TABLES ADG526A
A3 X X X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
A2 X X X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
Al X X X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A0 X X X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
EN X X 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
WR g X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RS 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
ON SWITCH Retains Previous Switch Condition NONE (Address and Enable Latches Cleared) NONE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
X = Don't Care
ADG527A
A2 X X X 0 0 0 0 1 1 1 1
Al X X X 0 0 1 1 0 0 1 1
A0 X X X 0 1 0 1 0 1 0 1
EN X X 0 1 1 1 1 1 1 1 1
WR g X 0 0 0 0 0 0 0 0 0
RS 1 0 1 1 1 1 1 1 1 1 1
ON SWITCH PAIR Retains Previous Switch Condition NONE (Address and Enable Latches Cleared) NONE 1 2 3 4 5 6 7 8
X = Don't Care
REV. B
-5-
ADG526A/ADG527A
PIN CONFIGURATIONS DIP, SOIC
S16 RS
LCCC
S16
PLCC
VDD
VDD
VSS
VSS
NC
RS
NC
S8
VDD 1 NC 2 RS 3 S16 4 S15 5 S14 S13 S12 S11
6 7
28 27 26 25 24
D VSS S8 S7 S6 S5
D
4
3
2
1
28 27 26 25 24
4
3
2
1
28 27 26 25 S7 24 S6
S15 5 S14
6
S7 S6 S5 S4 S3 S2 S1
S15 5 S14 6 S13 7 S12 8 S11 9 S10 10 S9 11
12 13 14 15 16 17 18
S8
23 S5 22 S4 21 S3 20 S2 19 S1
S13 7 S12 8 S11 9 S10 10 S9
11 12 13
ADG526A
TOP VIEW
(Not to Scale)
23 22 21 20 19
ADG526A
TOP VIEW
(Not to Scale)
ADG526A
23
22 S4 TOP VIEW 8 (Not to Scale) 21 S3 9 20 19 18 17 16 15
S2 S1 EN A0 A1
S10 10 S9 11 GND 12 WR 13 A3 14
14
15
16
17
18
GND
WR
A3
A2
A1 DA
D
A0 VSS
A3
A2
A1
A0
GND
WR
EN
NC = NO CONNECT
NC = NO CONNECT
S8B S8A
25 S7A 24 S6A 23 S5A 22 S4A 21 S3A 20 S2A 19 S1A 12 13 14 15 16 17 18
NC = NO CONNECT
4
3
DB
RS
A2
2
VDD
1
28 27 26
S7B 5
VDD 1 DB 2 RS 3 S8B 4 S7B 5 S6B S5B S4B S3B
6 7 8 9 28 27 26 25 24
DA VSS S8A S7A S6A S5A S4A
S6B 6 S5B 7 S4B 8 S3B 9 S2B 10 S1B 11
ADG527A
TOP VIEW
(Not to Scale)
ADG527A
23 22
GND
WR
NC
A2
A1
A0
20 19 18 17 16 15
S2A S1A EN A0 A1 A2
S2B 10 S1B 11 GND 12 WR 13 NC 14
NC = NO CONNECT
NC = NO CONNECT
-6-
EN
TOP VIEW (Not to Scale) 21 S3A
EN
REV. B
Typical Performance Characteristics-ADG526A/ADG527A
The multiplexers are guaranteed functional with reduced single or dual supplies down to 4.5 V.
700
1.9
600 500 400
VDD = 10.8V VSS = 0V VDD = 15V VSS = 0V
1.8
TRIGGER LEVEL - V
20
RON -
1.7
300 200 100 0 -20
1.6
1.5
-15 -10 -5 0 5 VD (VS) - V 10 15
5
6
7
8
9 10 11 12 SUPPLY VOLTAGE - V
13
14
15
TPC 1. RON as a Function of VD (VS): Dual Supply Voltage, TA = 25C
TPC 4. Trigger Levels vs. Power Supply Voltage, Dual or Single Supply, TA = 25C
700
800 700 600
600 500 400
VDD = +5V VSS = -5V
- ns
VDD = +10.8V VSS = -10.8V
TRANSITION
500 400 300 DUAL SUPPLY SINGLE SUPPLY
RON -
300 200 100 0 -20 VDD = +15V VSS = -15V -15 -10 -5 0 5 VD (VS) - V 10 15 20
t
200 100 5 6 7 8 9 10 11 12 SUPPLY VOLTAGE - V 13 14 15
TPC 2. RON as a Function of VD (VS); Single Supply Voltage, TA = 25C
TPC 5. tTRANSITION vs. Supply Voltage: Dual and Single Supplies, TA = 25C (Note: For VDD and / VSS / <10 V; V1 = VDD /VSS, V2 = VSS /VDD; See Test Circuit 6)
100 VDD = +16.5V VSS = -16.5V
1.0
0.8 LEAKAGE CURRENT - nA
10 ID (ON) ID (OFF) 1
IDD - mA
IS (OFF)
0.6
0.4
0.1
0.2
25
35
45
55 65 75 85 TEMPERATURE - C
95
105
115
125
5
6
7
8
9 10 11 12 13 SUPPLY VOLTAGE - V
14
15
16
17
TPC 3. Leakage Current as a Function of Temperature (Note: Leakage Currents Reduce as the Supply Voltages Reduce)
TPC 6. IDD vs. Supply Voltage: Dual or Single Supply, TA = 25 C
REV. B
-7-
ADG526A/ADG527A -Test Circuits
I DS
VDD VSS VDD VSS D A ID (ON) V2
V1
S VS RON = V1 I DS
D
V1 GND
EN
2.4V
Test Circuit 1. RON
Test Circuit 4. ID (ON)
VDD VSS
VDD
VSS
VDD
VSS EN DA 0.8V A A V2 GND
ADG527A
VDD VSS
IS (OFF) A GND EN
D 0.8V
V1
DB
V1
V2
IDIFF = IDA (OFF) - IDB (OFF)
Test Circuit 2. IS (OFF)
VDD VSS
Test Circuit 5. IDIFF
VDD
VSS
D EN 0.8V ID (OFF) A V2
V1
GND
Test Circuit 3. ID (OFF)
VDD VSS
VDD 3V 0V 50% ADDRESS DRIVE (VIN) VIN 50 A3 A2 A1 A0 90% OUTPUT 2.4V EN RS GND
VSS S1 V1
S2 THRU S15 S16 V2 OUTPUT D
ADG526A*
WR
90%
1M
35pF
tTRANSITION
tTRANSITION
*SIMILAR CONNECTION FOR ADG527A
Test Circuit 6. Switching Time of Multiplexer, tTRANSITION
-8-
REV. B
ADG526A/ADG527A
VDD VSS VDD 3V 0V ADDRESS DRIVE (VIN) VIN 50% OUTPUT 50 A3 A2 A1 A0 S1 S2 THRU S15 S16 5V VSS
ADG526A*
tOPEN
2.4V EN RS GND WR D
OUTPUT
1k
35pF
*SIMILAR CONNECTION FOR ADG527A
Test Circuit 7. Break-Before-Make Delay, tOPEN
VDD 3V ENABLE DRIVE (VIN) VSS
2.4V 50%
RS VDD A3 A2 A1
VSS S1 5V
0V 90% OUTPUT 10%
S2 THRU S16
A0
ADG526A*
D EN VIN GND WR
OUTPUT
tON
(EN)
tOFF
(EN)
1k
50
35pF
*SIMILAR CONNECTION FOR ADG527A
Test Circuit 8. Enable Delay, tON (EN), tOFF (EN)
VDD
VSS
VDD 2.4V 3V 0V 50% (WR) DRIVE (VIN) EN A3 A2
VSS S1 5V
S2 THRU S16 A1 20% OUTPUT A0
tON
(WR) RS
ADG526A*
D GND VIN 50 WR
OUTPUT
1k
35pF
*SIMILAR CONNECTION FOR ADG527A NOTE DEVICE MUST BE RESET PRIOR TO APPLYING WR PULSE
Test Circuit 9. Write Turn-On Time, tON (WR)
REV. B
-9-
ADG526A/ADG527A
VDD VSS VDD 2.4V 3V 0V 50% RS DRIVE (VIN) EN A3 A2 80% OUTPUT A1 A0 S1 S2 THRU S16 5V VSS
tOFF
(RS)
ADG526A*
WR RS GND VIN 50 D
OUTPUT
1k
35pF
*SIMILAR CONNECTION FOR ADG527A NOTE DEVICE WR MUST PULSED LOW PRIOR TO APPLYING RS PULSE
Test Circuit 10. Reset Turn-Off Time, tOFF (RS)
VDD VSS
VDD 3V VIN 0V VO QINJ = CL VO VO VS RS A0 A1 A2 A3 S1 EN VIN 50 GND
VSS RS 2.4V
ADG526A*
D CL 1nF WR VO
*SIMILAR CONNECTION FOR ADG527A
Test Circuit 11. Charge Injection
TERMINOLOGY
RON RON Match RON Drift IS (OFF) ID (OFF) ID (ON) VS (VD) CS (OFF) CD (OFF) CIN tON (EN) tOFF (EN) tTRANSITION tOPEN VINL VINH IINL (IINH) VDD VSS IDD ISS
Ohmic resistance between terminals D and S Difference between the RON of any two channels Change in RON versus temperature Source terminal leakage current when the switch is off Drain terminal leakage current when the switch is off Leakage current that flows from the closed switch into the body Analog voltage on terminal S or D Channel input capacitance for "OFF' condition Channel output capacitance for "OFF" condition Digital input capacitance Delay time between the 50% and 90% points of the digital input and switch "ON" condition Delay time between the 50% and 10% points of the digital input and switch "OFF" condition Delay time between the 50% and 90% points of the digital inputs and switch "ON" condition when switching from one address state to another "OFF" time measured between 50% points of both switches when switching from one address state to another Maximum input voltage for Logic "0" Minimum input voltage for Logic "1" Input current of the digital input Most positive voltage supply Most negative voltage supply Positive supply current Negative supply current -10- REV. B
ADG526A/ADG527A
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Plastic DIP (Suffix N) (N-28)
1.450 (36.830) 1.440 (35.580)
28 15
28-Lead Cerdip (Suffix Q) (Q-28)
1.49 (37.84) MAX
28 15
0.550 (13.970) 0.530 (13.470)
1 14
PIN 1
1 14
0.525 (13.33) 0.515 (13.08)
PIN 1 0.200 (5.080) MAX SEATING PLANE 0.105 (2.670) 0.096 (2.420)
0.060 (1.580) 0.020 (0.560)
0.606 (15.400) 0.594 (15.090)
GLASS SEALANT 0.22 (5.59) MAX
0.06 (1.52) 0.05 (1.27)
0.125 (3.175) MIN
0.62 (15.74) 0.59 (14.93)
0.18 (4.57) MAX
0.020 (0.508) 0.015 (0.381)
0.175 (4.450) 0.120 (3.050)
15 0
0.012 (0.306) 0.008 (0.203)
0.11 (2.79) 0.099 (2.28)
0.02 (0.5) 0.016 (0.406)
15 0
0.012 (0.305) 0.008 (0.203)
28-Terminal Leadless Ceramic Chip Carrier (Suffix E) (E-28A)
0.075 (1.91) REF 0.095 (2.41) 0.075 (1.90) 0.011 (0.28) 0.007 (0.18) R TYP 0.075 (1.91) REF
19 18 26 25 28 1 5
28-Terminal Plastic Leaded Chip Carrier (Suffix P) (P-28A)
0.180 (4.57) 0.165 (4.19) 0.056 (1.42) 0.042 (1.07)
26 25
0.100 (2.54) 0.064 (1.63)
0.300 (7.62) BSC 0.150 (3.51) BSC
4
0.015 (0.38) MIN 0.028 (0.71) 0.022 (0.56) 0.050 (1.27) BSC
11 12
0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07)
4 5 PIN 1 IDENTIFIER
0.025 (0.63) 0.015 (0.38) 0.021 (0.53) 0.013 (0.33)
BOTTOM VIEW
TOP VIEW
(PINS DOWN) 11 12 19 18
0.050 (1.27) BSC
0.032 (0.81) 0.026 (0.66)
0.430 (10.92) 0.390 (9.91)
0.055 (1.40) 0.045 (1.14)
0.200 (5.08) BSC
45 TYP
0.020 (0.50) R
0.456 (11.58) SQ 0.450 (11.43) 0.495 (12.57) SQ 0.485 (12.32)
0.040 (1.01) 0.025 (0.64) 0.110 (2.79) 0.085 (2.16)
28-Lead SOIC (R) Package (R-28)
0.512 (13.00) 0.496 (12.60)
28
15
0.300 (7.60) 0.292 (7.40)
1 14
0.419 (10.65) 0.319 (10.00)
0.104 (2.65) 0.093 (2.35)
0.012 (0.3) 0.004 (0.1)
0.0500 (1.27) BSC
0.019 (0.49) 0.014 (0.35)
0.013 (0.32) 0.009 (0.23)
0.005 (1.27) 0.016 (0.40)
REV. B
-11-
ADG526A/ADG527A Revision History
Location Data Sheet changed from REV. A to REV. B. Page
Edits to Specifications Table, Dual Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Edits to Specifications Table, Single Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Removal of one PIN CONFIGURATION and diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
C01532-0-2/02(B) PRINTED IN U.S.A.
-12-
REV. B

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